In microelectromechanical systems (MEMS) and semiconductor devices, high aspect ratio trenches are common features. For example, MEMS rotational rate sensors and accelerometers, micro-fluidic mixing devices, micro-mirrors, micro-pillars, deep trench capacitors and isolation for high frequency circuitry, and power devices all include high aspect ratio features.
Conventionally, high aspect ratio features are formed with cryogenic deep reactive ion etching (cryogenic DRIE) processing. For these particular and many other applications, high surface finish of the resulting Si structure is required, and therefore cryogenic DRIE of Silicon is highly favorable. Chemicals and plasmas for etching the high aspect ratios are selected based on the material being etched to form the structures. For example, SF6/O2 plasma is often used for anisotropic etching of high aspect ratio trenches in silicon. Forming high aspect ratio structures is dependent, in part, on selecting a masking material with high etch selectivity to the material being etched in the cryogenic DRIE plasma. Additionally, the mask material should apply conformally to the substrate being etched and deposited at temperatures that do not damage other components on the substrate. Conventionally, for deep cryogenic etching silicon in SF6/O2, etch mask materials have included silicon oxide, silicon nitride, aluminum, chromium, and photoresist. With silicon oxide as a mask material selectivity may reach 100:1 when etching silicon in an SF6/O2 plasma. That is, for every 1 μm of silicon oxide etched in the SF6/O2 plasma, 100 μm of silicon is etched.
In order to realize innovative solutions in many modern electronic devices, structures with smooth surface finish are required. At the present moment achieving the high aspect ratio structures using known values of selectivity of etching material, thick masks are required. The increasing of the mask thickness creates additional difficulties in manufacturing of high aspect ratio structures. Among those difficulties, the most common include: achieving the high angel slopes of the masks which directly affect the profile of the etching; most of the existing polymer masks have their tendency of cracking at low temperatures; and good uniformity is difficult to achieve with thick masks. Additionally, thick etch masks reduce the resolution of the pattern transferred into the etch mask and into the substrate and impose further limitations on the minimum features that may be transferred (e.g., mask critical dimension) and overall uniformity. The sidewall profile of the high aspect ratio features in the substrate degrades with thicker etch masks. Thus, a thin etch mask layer is preferred for high aspect ratio etching.
One previous solution is the use of alumina (aluminum oxide) as an etch mask for high aspect ratio etching. Alumina has a selectivity of over 5000:1 for etching silicon in an SF6/O2 plasma. However, there are still some problems with film cracking, sensitivity to humidity, and excessive base solubility, in addition to the need of a special methods to deposit thin and conformal layers of alumina (i.e., Atomic Layer Deposition) cause problems in using alumina as an etch mask. Additionally, the stripping of alumina for post-etch processing is difficult and requires hydrofluoric (HF) acid or other exotic etches, which may cause damage to the structures already present on the substrate such as underlying complimentary metal-oxide-semiconductor (CMOS) transistors.
Other previous solutions include metal masks such as aluminum, copper, chromium and nickel, which have high selectivity with respect to silicon in SF6/O2 plasmas. However metal films are electrically conductive, which may result in electric field effect, undercut, and profile notching. Etching of silicon substrates with metal masks may require dedicated chambers because of the contaminating effects of re-deposition of the metal masks, which negatively affects the etching quality and chamber lifetime. Additionally, metal films may require exotic etchants (such as HNO3 for copper or H2SO4 for chromium) for pattern transfer into the etch mask or sputtering at high temperatures as in the case for aluminum, which might not be suitable for CMOS post-processing. Re-sputtering and re-deposition of metal masking material causes micrograss or micromasking on the silicon substrate, which may result in process contamination and reduce the sticking coefficient of the passivation layer on the sidewalls of the trench and may lead to isotropic profiles.
Another previous solution uses photoresist as the etch mask. However, photoresists are inadequate for cryogenic processes because they crack at sub-zero temperatures. Furthermore, photoresists have etch selectivity as low as 40:1 to silicon in an SF6/O2 plasma. The low selectivity often restricts the aspect ratio of features etched with photoresist etch masks to 300 μm and places limits on the lateral dimensions.